Flip-chip assemblies are formed by combining two separate chips. Usually one of the chips contains spacers that offset the facing surfaces of each of the chips. For micro-electromechanical systems (MEMS) devices, at least one of the chips is often formed using silicon-on-insulator (SOI) technology. In an SOI chip, the top layer of silicon is electrically isolated from the underlying silicon wafer by a silicon oxide layer. Once the two chips are bonded together, it is often desired to electrically connect at least one layer of the bottom chip and one layer of the top chip.
Prior art methods for electrically connecting layers of such chips that are so connected together in a flip-chip arrangement when at least one of the chips has an insulating layer running through it include a) solder bumps between the chips, b) bond pads on the top that are connected to counterpart bond pads on the bottom using wires, and c) using conductive epoxy in between the chips and/or a at the edge of the chips to connect all of the layers of the top chip to at least one layer of the bottom chip. Should more than one layer of a single chip need to be connected to the same layer of the other chip, this may be achieved by using vias that run through the insulating layer to connect the two.
These prior art methods are disadvantageous, because a) solder bumps require too much preparation, e.g., so-called “under bump metalizaton”, of the chips, b) bond pads connect only one layer of the top chip unless vias are employed, and the use of vias significantly complicates the processing of the top chip, and c) conductive epoxy outgasses chemicals which will redeposit themselves on the structure of the MEMS device if the MEMS device is hermetically sealed, as is often the case, thus degrading the MEMS device.